Senior Design Verification Engineer

HPR is a leading provider of high-performance and ultra-low latency electronic trading and capital markets infrastructure solutions offered as a managed service. Our cutting-edge technology is used by tier-1 financial institutions to monitor and execute trades rapidly and efficiently. As we continue to innovate and grow, we’re searching for a forward-thinking Senior Design Verification Engineer to help us build the future of capital markets infrastructure.

As a Senior Design Verification Engineer at HPR, you will:

• Verify and maintain high-performance FPGA compute and networking systems used in electronic trading
• Own the verification process from specification, test planning, and testbench development through execution and coverage closure
• Partner with design engineers to review and execute comprehensive test plans
• Create and maintain reusable verification components and testbenches written in SystemVerilog
• Lead and mentor junior engineers, promoting our culture of continuous learning and collaboration
• Contribute to improving our verification processes, tools, and methodologies

Required Qualifications

• BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related
• 5+ years of experience in design verification for FPGAs or ASICs
• Proficiency in SystemVerilog for verification <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815&q